1. Technical Field
This disclosure relates to a semiconductor memory device, and more particularly, to a memory expansion structure in a multi-path accessible semiconductor memory device suitable to be employed to a mobile communication system.
2. Discussion of Related Art
In general, a semiconductor memory device having multiple access ports is called a multi-port memory. In particular, a memory device having two access ports is called a dual port memory. A typical dual port memory is an image processing video memory having a random access memory (RAM) port accessible in a random sequence and a serial access memory (SAM) port accessible in a serial sequence, which is widely known in the present field.
In this disclosure, a dynamic random access memory (DRAM) for reading and writing a shared memory region of a memory cell array made up of DRAM cells through multiple access ports without the SAM port, unlike a configuration of a video memory, will be herein referred to as a multi-path accessible semiconductor memory device in order to distinguish from the multi-port memory.
The use of electronic systems in current societies has expanded ubiquitously. In order to insure high-speeds and smooth functionality or operation in portable electronic systems and electronic appliances, such as notebook computers, hand-held phones and personal digital assistants (PDAs), for example, manufacturers have used multiprocessor systems as shown in FIG. 1.
Referring to FIG. 1, a first processor 10 is connected with a second processor 12 through a connection line L10. A NOR memory 14 and a first DRAM 16 are coupled to the first processor 10 through set buses B1 through B3. A second DRAM 18 and a NAND memory 20 are coupled to the second processor 12 through set buses B4 through B6. The first processor 10 may have a modem function for modulating and demodulating communication signals. The second processor 12 may have an application function for processing communication data or executing games, providing entertainment, and so on. The NOR memory 14 has a NOR cell array structure. The NAND memory 20 has a NAND cell array structure. Both are non-volatile memories having transistor memory cells with floating gates, and may be used to store data, such as a native code or data of the portable appliance that should not be erased even when power is turned off. The first and second DRAMs 16 and 18 act as main memories for the first and second processors, respectively.
However, in the multiprocessor system as in FIG. 1, the DRAMs are correspondingly allocated to both the processors, and relatively low-speed interfaces, such as universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI), static random access memory (SRAM) interfaces. Hence, it is difficult to secure a sufficient data transmission speed, size is increased and memory component costs are increased. A scheme for reducing an occupied size, enhancing a transmission speed, and decreasing the number of employed memories is shown in FIG. 2. A multiprocessor system of FIG. 2 is characterized in that one DRAM 17 is connected to first and second processors 10 and 12 through buses B1 and B2 respectively, in contrast to that of FIG. 1. In order for each of the processors to access one DRAM 17 through two separate paths, two ports are required on the DRAM 17. However, the DRAM 17 is generally a device having a single input/output path part 16 and a single port PO, as shown in FIG. 3.
FIG. 3 shows a structure of the general DRAM. A memory cell array 1 includes first to fourth banks 3, 4, 5 and 6, each of which includes a row decoder 8 and a column decoder 7. An upper input/output sense amplifier and driver 13 is operatively connected with the first bank 3 and the third bank 5 through multiplexers 11 and 12. A lower input/output sense amplifier and driver 15 is operatively connected with the second bank 4 and the fourth bank 6 through multiplexers 13 and 14.
For example, when a memory cell in the first bank 3 is selected to read data stored in the selected memory cell, a process of outputting the read data is as follows. First, the data of the memory cell, which is sensed and amplified by a bit line sense amplifier in the cell array after a selected word line is activated, is transmitted to a local input/output line pair 9 by activation of a corresponding column select line (CSL). The data transmitted to the local input/out line pair 9 is transmitted to a global input/output line pair 10 by a switching operation of a first multiplexer 21, and the second multiplexer 11 connected to the global input/output line pair 10 transmits the data of the global input/output line pair 10 to the upper input/output sense amplifier and driver 13. The data, which is again sensed and amplified by the upper input/output sense amplifier and driver 13, is output to a data output line L5 through the path part 16. Similarly, when data stored in the memory cell of the fourth bank 6 is read, the data is output to an output terminal DQ through a multiplexer 24, the multiplexer 14, the lower input/output sense amplifier and driver 15, the path part 16, and the data output line L5 in that order. Thus, the DRAM 1 of FIG. 3 has a structure in which two banks share one input/output sense amplifier and driver. In addition, the DRAM 1 is a single port memory in which the data is input/output through one port PO. Consequently, the DRAM 1 of FIG. 3 may be used in the system of FIG. 1, but it is difficult or impossible to be used in the multiprocessor system of FIG. 2 due to the structures of the memory bank and port.
Referring to FIG. 4, there is shown a multiprocessor system in which a memory array 35 has first, second and third portions. The first portion 33 of the memory array 35 is accessed only by a first processor 70 through a port 37, the second portion 31 is accessed only by a second processor 80 through a port 38, and the third portion 32 is accessed by both the first and second processors 70 and 80. Sizes of the first and second portions 33 and 31 of the memory array 35 can be flexibly varied depending on operation loads of the first and second processors 70 and 80. The memory array 35 may be realized as a memory or a disk storage.
When implementing the third portion 32, shared by the first and second processors 70 and 80 in the DRAM structure, several problems may arise. For example, a technique of arranging the memory regions and input/output sense amplifier in the memory array 35 and controlling a proper read/write path with respect to each port is needed. Furthermore, a processor may require the memory region to be extended. For example, a storage capacity (or a memory capacity) of data that the second processor 80 can read or write in order to provide moving pictures or various multimedia needs increasing.
Thus, in the multiprocessor system having at least two processors, there is a need for a more appropriate solution for sharing the shared memory region allocated in the DRAM memory cell array, as well as an improved method of making it possible to additionally extend the capacity of memory as much as desired in the system when the specific processor requires to extend the memory region.